Conventional integrated circuit memories contain individual memory cells arranged in an array of rows and columns. Occasionally, fabrication defects render one or more cells inoperative. To boost production yields, several redundant rows and columns of cells are integrated into the memory array to be used as substitutes for the defective rows or columns. After identifying the defective row or column, a redundant row or column is substituted for the row or column containing the defect. This substitution requires the programmable devices, such as fuses or antifuses, to identify the defective rows or columns for which a redundant row or column is to be substituted.
Antifuses are capacitive-type structures, an example of which is shown in FIG. 1. As shown in FIG. 1, an electronic circuit 2 contains an antifuse 4 which includes a pair of conductive plates 6 and 8 and a dielectric material 9 between the plates. The conductive plates 6, 8 may be made from doped silicon, polysilicon, metal or another conductive material with similar properties. The dielectric material 9 may be made from oxide, nitride, nitride-oxide, oxide-nitride-oxide, undoped amorphous silicon, or equivalents thereof In an unprogrammed state, the antifuse 4 is non-conductive and has a resistance of over 1 mega-ohm across the plates 6, 8. To program the antifuse 4, a relatively high electric field is applied across the plates 6, 8. The high electric field causes the breakdown and melting of a portion of the dielectric material 9, and the two plates 6, 8 of the antifuse 4 flow, contacting each other and creating a low-resistance path. Essentially, the breakdown of the dielectric material 9 occurs at an area in which the composition of the material is most defective. Therefore, blown antifuses conduct and unblown antifuses do not conduct.
As mentioned above, fuses (not shown) are also used to identify defective rows or columns in a memory device for which a redundant row or column is to be substituted. Fuses are basically conductive paths that are opened and thus made non-conductive by applying a sufficiently large voltage and current to the fuse.
FIG. 2A shows a part of a conventional substitute memory cell enabling circuit array 10. The enabling circuit array 10 shown in FIG. 2A is capable of selecting up to three substitute rows or columns using three respective banks 12, 14, 16 of programming circuits 20a, b . . . n. It will be understood, however, that a lesser or greater number of banks 12, 14, 16 may be used to enable a lesser or greater number of substitute rows or columns.
The number of programming circuits 20 in each bank 12, 14, 16 corresponds to the number of bits in an address designating the defective row or column. The corresponding programming circuits 20a, b, . . . n in each bank 12, 14, 16 receive a respective address bit A.sub.0, A.sub.1, . . . A.sub.n. The address received in the address bits A.sub.0, A.sub.1, . . . A.sub.n of the bank 12, 14, 16 are not necessarily the same as the row or column address of the defective row or column. All of the programming circuits 20a, b, . . . n in each bank 12, 14, 16 are enabled by a respective NMOS bank select transistor 22, 24, 26. The conductive state of each bank select transistor 22, 24, 26 is controlled by a respective enable inputs En.sub.0, En.sub.1, En.sub.2.
Each programming circuit 20 also includes an antifuse 4 having a air of plates 6, 8 as explained above with reference to FIG. 1. The plate 6 of each antifuse 4 is connected to a circuit ground node 30. The circuit ground nodes 30 of all of the programming circuits 20 are connected to each other and to a circuit ground C.sub.GND input. The other plate 8 of the antifuse 4 is connected through a voltage clamping transistor 36 and an antifuse select transistor 38 to the drain of one of the bank select transistors 22, 24, 26. The gate of each voltage clamping transistor 36 is coupled to an elevated supply voltage V.sub.CCP. The elevated supply voltage V.sub.CCP is normally generated from a supply voltage V.sub.CC using a charge pump or similar circuit, although it may be generated from any source. The gate of each antifuse select transistor 38 in one bank is connected to the gates of corresponding antifuse select transistors 38 in other banks. Thus, for example, the gates of the antifuse select transistors 38 in the programming circuits 20a are all connected to each other and to the A.sub.0 input.
The manner in which the antifuses 4 are programmed to correspond to the addresses of defective rows or columns will now be explained. Initially, the antifuse select transistors 38 and the bank select transistors 22, 24, 26 are all OFF. When the memory cell enabling array 10 is ready for programming, a relatively large programming voltage is applied to the C.sub.GND terminal and a logic "1" is applied to one of the enable inputs En.sub.0 -En.sub.2 to turn on the corresponding bank select transistor 22, 24, 26. The bank select transistor, for example transistor 22, pulls the source of each antifuse select transistor 38 in the bank 12 to ground. At this time, the plate 6 of the antifuse 4 in each programming circuit 20 in the bank 12 is coupled to the relatively high programming voltage while the plate 8 in each programming circuit 20 is isolated from ground by its respective antifuse select transistor 38.
The final programming step is turning ON the antifuse select transistors 38. A pattern of address bits A.sub.0 -A.sub.n is applied to the gates of the antifuse select transistors 38 in all of the programming circuits 20. The antifuse select transistors 38 receiving a high gate voltage are turned ON, thereby completing the circuit path from the plate 8 of the antifuse 4 to ground in the enabled bank 12 in which the bank select transistor 22 is turned ON. As a result, the full magnitude of the programming voltage on the C.sub.GND terminal is applied between the plates 6, 8 of selected antifuses 4 in the bank 12. The resulting electric field causes a breakdown of the dielectric material 9, thereby forming a low-resistance path across the antifuses 4. Although the antifuse select transistors 38 are selectively turned ON in the remaining banks 14, 16, the plates 8 of the antifuses in these banks are isolated from ground by the OFF bank select transistors 14, 16.
After the substitute memory cell enabling array 10 has been programmed as described above, it is used to identify row or column addresses corresponding to defective rows or columns for which a substitute row or column must be used. A sensing circuit (not shown) determines whether antifuses 4 have been blown in the pattern of the address by applying the bits of the address to respective antifuses 4 in all of the banks 12, 14, 16. The sensing circuit (not shown) uses a logic circuit to combine the resulting signals from all of the antifuses 4 in each bank to determine if the antifuses 4 in any of the banks 12, 14, 16 are programmed in the same pattern as the address. If the address matches one of the addresses that has been programmed into the antifuses 4, the output of the logic gate changes state and enables a substitute row or column of memory cells.
One of the inherent problems with the prior art substitute memory cell enable array 10 shown in FIG. 2A is the unintended programming of antifuses 4. This problem is best explained with reference to FIGS. 2B and 2C. FIG. 2B shows the programming circuit 20 in a non-selected bank 14 during programming of a selected bank 12, while FIG. 2C shows the voltages at various nodes in the circuit of FIG. 2B.
During programming of the antifuse 4, the programming voltage applied to the circuit ground node 30 is applied to the plate 6 of the antifuse 4. Since the plate 8 is isolated from ground at this time because the antifuse select transistor 38 is OFF, the voltage on the plate 8 follows the rise of the voltage on the plate 6. At time t.sub.0, the A.sub.0 input to the gate of the antifuse select transistor 38 goes high to program the antifuse 4 in the corresponding programming circuit 20a of the enabled bank 12. However, since the gates of all antifuse select transistors 38 in corresponding programming circuits 20a are connected to each other, the antifuse select transistor 38 in the non-selected bank 14 also turns ON. Although the bank select transistor 24 of the non-selected bank 14 is OFF, the source of the transistor 38 is nevertheless coupled to ground by a parasitic capacitance 40 due to the relatively long interconnection between the drain of the bank select transistor 24 and the source of the antifuse select transistor 38. As a result, the voltage on the plate 8 is pulled to V.sub.O at time t.sub.0, and gradually increases as the parasitic capacitance 40 charges. The voltage V.sub.O is substantially equal to the voltage V.sub.CC applied to the gate of the transistor 38 less its threshold voltage V.sub.T. As the voltage on the parasitic capacitance 40 increases, the voltage at a node 44 increases to V.sub.CCP -V.sub.T, where V.sub.T is the threshold voltage of the transistor 36, as shown in FIG. 2C. When the voltage at node 44 reaches this level, the transistor 36 turns OFF. The voltage on a bank select node 46 across the parasitic capacitance 40 eventually rises to V.sub.CC -V.sub.T, where V.sub.T is the threshold voltage of the transistor 38, as also shown in FIG. 2C. At this point, the transistor 38 turns OFF.
It is significant that, up until the time that the transistors 36, 38 turn OFF, there is a substantial voltage across the antifuse 4 and a current path from the circuit ground node 30 to ground through the parasitic capacitance 40, the transistors 36, 38 and the antifuse 4. As a result, sufficient current can flow through the antifuse 4 to partially or completely blow the antifuse 4, or otherwise overstress the dielectric material 9 of the antifuse 4.
If an antifuse 4 is inadvertently programmed as described above, it may be possible to detect the error during testing of the memory device containing the substitute memory cell enabling array 10. However, the inadvertent programming of the antifuse 4 may be less than complete. In particular, the voltage inadvertently applied to an antifuse 4 as explained above may stress the dielectric material 9 in the antifuse 4, but not sufficiently to cause the antifuse to become sufficiently conductive to be perceived as being programmed. However, once stressed, the dielectric material 9 in the antifuse 4 may break down over time thus transitioning from a state that is perceived to be non-conductive to a state that is perceived to be conductive. Also, a partially programmed antifuse may be perceived as non-conductive under some conditions, such as supply voltage or temperature values, but be perceived as conductive under other conditions. Consequently, an antifuse 4 that is not intended to be programmed may be perceived as non-conductive during testing of an integrated circuit, but may be perceived as conductive during use of the integrated circuit.
Although the above discussion relates to the use of antifuses 4 in the substitute memory cell enable array 10, it is also applicable to other types of electrically programmed programming elements, such as fuses. In particular, a voltage applied to a the C.sub.GND input to program a fuse (not shown) would result in a current through the fuse, the transistor 36, 38 and an ON bank select transistor, such as transistor 22, of the selected bank 12. However, the voltage applied to the fuses in non-selected banks, for example bank 14, would also be coupled through the transistors 36,38 in those banks to the parasitic capacitances 40 of the interconnections of the OFF bank select transistors 24, 26. The current flowing through the fuses to charge the parasitic capacitances 40 may, in some cases, be sufficient to completely or partially program the fuses in the non-selected banks 14, 16.